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STM6510
Dual push-button Smart ResetTM with capacitor-adjustable delays
Features
Dual Smart ResetTM push-button inputs with capacitor-adjustable extended reset setup delay (tSRC) Capacitor-adjustable reset pulse duration (tREC) Power-on reset - RST active-low, open-drain Factory-programmable thresholds to monitor VCC in the range of 1.575 to 4.625 V typ. Operating voltage 1.0 V (active-low output valid) to 5.5 V Low supply current (1.4 A) Operating temperature: industrial grade -40 C to +85 C TDFN8 package: 2 mm x 2 mm x 0.75 mm RoHS compliant TDFN8 (DG) 2 mm x 2 mm

Applications

Mobile phones, smartphones e-books MP3 players Games Portable navigation devices Any application that requires delayed reset push-button(s) response for improved system stability
February 2010
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www.st.com 1
Contents
STM6510
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 1.2 1.3 Smart ResetTM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 STM6510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Smart ResetTM push-button inputs (SR0, SR1) . . . . . . . . . . . . . . . . . . . . 9 Adjustable delay of Smart ResetTM input (SRC pin) . . . . . . . . . . . . . . . . 9 Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Adjustable reset timeout (TRECADJ pin) . . . . . . . . . . . . . . . . . . . . . . . . 10
2 3 4 5 6 7 8
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 tSRC programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 tREC programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Possible VCC voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TDFN - 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . 18 Parameter for landing pattern - TDFN - 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 19 Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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List of figures
STM6510
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Single-button Smart ResetTM typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Dual-button Smart ResetTM typical hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply current (ICC) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Smart ResetTM delay (tSRC) vs. temperature, CSRC = 0.56 F . . . . . . . . . . . . . . . . . . . . . . 11 Reset timeout period (tREC) vs. temperature, CtREC = 0.01 F . . . . . . . . . . . . . . . . . . . . . 12 Reset threshold (VRST) vs. temperature, "S" threshold option, VCC falling. . . . . . . . . . . . . 12 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TDFN - 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . 18 Landing pattern - TDFN - 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 19 Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package marking, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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Description
1
1.1
Description
Smart ResetTM devices
The Smart ResetTM device family STM65xx provides a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. This is done by implementing an extended Smart ResetTM input delay (tSRC). Once the valid Smart ResetTM input levels and setup delay are met, the device generates an output reset pulse with userprogrammable timeout period (tREC). The typical application hookup shows that the dual Smart ResetTM inputs can be also connected to the applications interrupt to allow the control of both the interrupt pin and the hard reset functions. If the push-buttons are closed for a short time, the processor is only interrupted. If the system still does not respond properly, holding the push-buttons for the extended setup time (tSRC) causes a hard reset of the processor through the reset output. The Smart ResetTM feature helps significantly increase system stability. The STM65xx family of Smart ResetTM devices consists of low-current microprocessor reset circuits targeted at applications such as MP3 players, portable navigation devices or mobile phones, generally any application that requires delayed reset push-button(s) response for improved system stability. The STM65xx devices feature single or dual Smart ResetTM inputs (SRx). The delayed Smart ResetTM setup time (tSRC) options are adjustable by adding an external capacitor on the SRC pin or selectable by three-state logic. The delayed setup period ignores switch closures shorter than tSRC, thus preventing undesired resets. The STM65xx devices have active-low (optionally active-high) open-drain reset (RST) output(s) with or without an internal pull-up resistor or push-pull as output options, with or without the power-on reset function. Some devices also have an undervoltage monitoring feature: the reset output is also asserted when the monitored supply voltage VCC drops below the specified threshold. The reset output remains asserted for the reset timeout period (tREC) after the monitored supply voltage goes above the specified threshold.
1.2
STM6510
The STM6510 has two combined Smart ResetTM inputs (SR0 and SR1) with Smart ResetTM setup delay (tSRC) programmed by an external capacitor on the SRC pin. An additional STM6510 feature is adjustable output reset pulse time tREC by adding an external capacitor (CtREC). Additionally, the VCC is monitored and if it drops below the selected VRST threshold, the reset output goes active and remains active while VCC is below the VRST threshold, plus the defined duration of the reset pulse tREC.
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Description Figure 1. Logic diagram
VCC
STM6510
SR0 SR1 SRC STM6510 RST TRECADJ
VSS
AM00389a
Figure 2.
Pin connections
RST VSS SR1 NC
1
8 STM 6510 7 6 5
VCC SR0 TRECADJ SRC
AM00390
2 3 4
Table 1.
Symbol RST SR0 SR1 SRC TRECADJ
Signal names
Input/output Output Input Input Input Input Description Reset output, active-low (open-drain). Primary push-button Smart ResetTM input. Active-low, internal 65 k pull-up resistor to VCC. Secondary push-button Smart ResetTM input. Active-low, internal 65 k pull-up resistor to VCC. Smart ResetTM input delay setup control. Connect an external capacitor to this pin to adjust the delay setup time (tSRC). Input pin for tREC reset pulse duration adjustment. Connect an external capacitor (CtREC) to this pin to determine tREC. Supply voltage input. Power supply for the device and an input for the monitored supply voltage. A 0.1 F decoupling ceramic capacitor is recommended to be connected between VCC and VSS pins. Ground No connect (not bonded); should be connected to VSS.
VCC VSS NC
Supply Supply
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STM6510 Figure 3.
VCC
Description Block diagram
VRST COMPARE
65 k
65 k tREC generator RST
SR0 SR1 SRC
Logic
TRECADJ CtREC
AM00391a
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Description Figure 4. Single-button Smart ResetTM typical hookup
VCC
STM6510
VCC TRECADJ CtREC
100 k RST SRC CSRC SR1 SR0 INT/ NMI RESET
VCC
STM6510
MCU
VSS
VSS
PUSH-BUTTON SWITCH
AM04870v1
Note:
When only one Smart ResetTM input push-button is used, tie both the SR inputs together. Figure 5. Dual-button Smart ResetTM typical hookup
VCC
VCC TRECADJ CtREC
100 k RST SRC CSRC SR1 INT/ NMI RESET VCC
STM6510
MCU
SR0 VSS
VSS
PUSH-BUTTON SWITCH
PUSH-BUTTON SWITCH
AM004871v1
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STM6510
Description
1.3
1.3.1
Pin descriptions
Power supply (VCC)
This pin is used to provide the power to the Smart ResetTM device and to monitor the power supply. A 0.1 F decoupling ceramic capacitor is recommended to be connected between the VCC and VSS pins.
1.3.2
Ground (VSS)
This is the supply ground for the device.
1.3.3
Smart ResetTM push-button inputs (SR0, SR1)
Both SR0 and SR1 need to be held active at the same time for at least tSRC to activate the reset output pulse. Include an internal 65 k pull-up resistor to VCC for each input. Figure 6. Timing waveforms
tSRC SR0 tREC
SR1
RST
AM00393
1.3.4
Adjustable delay of Smart ResetTM input (SRC pin)
This pin controls the setup time before the push-button action is validated by the reset output. It is connected to an external capacitor (CSRC), which is tied to ground to provide the desired value of setup time (tSRC). Calculated tSRC and CSRC examples are given in Table 2. Refer also to Table 6. Table 2. tSRC programmed by an ideal external capacitor
Setup delay tSRC [s](1)(2) Min. 2 3 6 10 Typ. 3 4.5 9 15 Max. 4 6 12 20 Closest common CSRC value [F] 0.22 0.33 0.56 1
Calculated CSRC value [F] 0.2 0.3 0.6 1
1. Example calculations based on an ideal capacitor. During application design and component selection it should be considered that the current flowing into the external tSRC programming capacitor (CSRC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB environment should be used to prevent tSRC accuracy from being affected. A recommended minimum value of CSRC is 0.01 F. 2. In case of repeated activations of the tSRC counter, an interval of 10 ms min. is needed between the activations to fully discharge CSRC, so that the next tSRC is as specified.
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Description
STM6510
1.3.5
Reset output (RST)
RST is active-low, open-drain.
1.3.6
Adjustable reset timeout (TRECADJ pin)
The reset timeout (tREC) is adjustable by connecting an external capacitor CtREC to this pin. Calculated tREC and CtREC examples are given in Table 3. Refer also to Table 6. Table 3. tREC programmed by an ideal external capacitor
tREC [ms](1)(2) Min. 10 20 100 140 280 560 1120 Typ. 15 30 150 210 420 840 1680 Max. 20 40 200 280 560 1120 2240 Closest common CtREC value [F] 0.001 0.0022 0.01 0.015 0.027 0.056 0.1
Calculated CtREC value [F] 0.001 0.002 0.01 0.014 0.028 0.056 0.112
1. Example calculations based on an ideal capacitor. During application design and component selection it should be considered that the current flowing into the external tREC programming capacitor (CtREC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB environment should be used to prevent tREC accuracy from being affected. A recommended minimum value of CtREC is 0.001 F. 2. In case of repeated activations of the tREC counter, an interval of 10 ms min. is needed between tREC intervals to fully discharge CtREC, so that the next tREC is as specified.
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Typical operating characteristics
2
Figure 7.
Typical operating characteristics
Supply current (ICC) vs. temperature
2.4 2.2 2 1.8 1.6 1.4 ICC [A] 1.2 1 0.8 0.6 0.4 0.2 0 -60 -40 -20 0 20 5.5 V 40 Temperature [C] 3.3 V 5V 3V
AM04876v1
60
80
100
120
140
Figure 8.
Smart ResetTM delay (tSRC) vs. temperature, CSRC = 0.56 F
12
11
10
tSRC [s]
9
8
7
6 -60 -40 -20 0 20 5.75 V 40 Temperature [C] 5.5 V 3.3 V
AM04877v1
60
80
100
120
140
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Typical operating characteristics Figure 9. Reset timeout period (tREC) vs. temperature, CtREC = 0.01 F
200 190 180 170 160 tREC [ms] 150 140 130 120 110 100 -60 -40 -20 0 20 40 Temperature [C] 5.75 V 5.5 V 3.3 V 60 80 100 120
STM6510
140
AM04878v1
Figure 10. Reset threshold (VRST) vs. temperature, "S" threshold option, VCC falling
2.99
2.97
2.95
VRST [V]
2.93
2.91
2.89
2.87
2.85 -60 -40 -20 0 20 40 Temperature [C] 60 80 100 120 140
AM04879v1
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Maximum ratings
3
Maximum ratings
Stressing the device above the rating listed in the Table 4: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronicsTM SURE Program and other relevant quality documents. Table 4.
Symbol TSTG TSLD(1)
Absolute maximum ratings
Parameter Storage temperature (VCC off) Lead solder temperature for 10 seconds Thermal resistance (junction to ambient) Input or output voltage Supply voltage TDFN8 Value -55 to +150 260 149.0 -0.3 to VCC +0.3 -0.3 to 7 Unit C C C/W V V
JA
VIO VCC
1. Reflow at peak temperature of 260 C. The time above 255 C must not exceed 30 seconds.
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DC and AC parameters
STM6510
4
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the Table 6: DC and AC characteristics that follow, are derived from tests performed under the Measurement Conditions summarized in Table 5: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and measurement conditions
Parameter VCC supply voltage Ambient operating temperature (TA) Input rise and fall times Input pulse voltages Input and output timing ref. voltages Value 1.0 to 5.5 -40 to +85 5 0.2 to 0.8 VCC 0.3 to 0.7 VCC Unit V C ns V V
Figure 11. AC testing input/output waveforms
0.8 VCC 0.2 VCC 0.7 VCC 0.3 VCC
AM00478
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STM6510 Table 6.
Symbol VCC ICC
DC and AC parameters DC and AC characteristics
Parameter Test conditions(1) Reset output valid - active-low VCC = 5.0 V VCC = 3.0 V
(3)
Min. 1.0
Typ.(2)
Max. 5.5
Units V A A
Supply voltage range Supply current (VCC)
1.5 1.4
2.4
VCC 4.5 V, sinking 3.2 mA VOL Reset output voltage low VCC 3.3 V, sinking 2.5 mA VCC 1.0 V, sinking 0.1 mA -40 to +85 C VRST VCC undervoltage reset threshold (refer to Table 7) 25 C L, M VHYST Hysteresis of VRST VCC to reset delay(4) tREC(4) User-adjustable reset timeout period on RST. Refer to Table 3. T, S, R, Z, Y, W, V VCC falling from (VRST + 100 mV) to (VRST - 100 mV) at 10 mV/s VRST -2.5% VRST -2.0% VRST VRST 0.5% 1% 20
0.3 0.3 0.3 VRST +2.5% VRST +2.0%
V V V V V
s
10 000 x 15 000 x 20 000 x CtREC CtREC CtREC (F) (F) (F)
ms
Smart ResetTM inputs tSRC(5) VIL VIH RPUI User-adjustable delayed Smart ResetTM setup time. Refer to Table 2. SR0, SR1 input voltage low SR0, SR1 input voltage high Internal pull-up resistor, SR0, SR1 inputs 0.7 VCC 65 10 x CSRC (F) 15 x CSRC (F) 20 x CSRC (F) 0.3 VCC s V V k
1. Valid for ambient operating temperature: TA = -40 to +85 C; VCC = 1.0 to 5.5 V (except where noted). 2. Typical value is at 25 C and VCC = 3.3 V unless otherwise noted. 3. For devices with VRST < 3.0 V. 4. Guaranteed by design. 5. Input glitch immunity is equal to tSRC (when both SR inputs are low, otherwise infinite).
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DC and AC parameters Table 7. Possible VCC voltage thresholds
2.5% (-40 C to +85 C) Typ. Min. 4.625 4.375 3.075 2.925 2.625 2.313 2.188 1.665 1.575 4.509 4.266 2.998 2.852 2.559 2.255 2.133 1.623 1.536 Max. 4.741 4.484 3.152 2.998 2.691 2.371 2.243 1.707 1.614 Min. 4.533 4.288 3.014 2.867 2.573 2.267 2.144 1.632 1.544 Max. 4.718 4.463 3.137 2.984 2.678 2.359 2.232 1.698 1.607 2.0% (25 C)
STM6510
VCC voltage threshold VRST L (falling) M (falling) T (falling) S (falling) R (falling) Z (falling) Y (falling) W (falling) V (falling)
Unit V V V V V V V V V
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Package mechanical data
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
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Package mechanical data Figure 12. TDFN - 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline
D A B
STM6510
PIN 1 INDEX AREA
E
0.10 C 2x
0.10 C 2x TOP VIEW 0.10 C
A
A1
SEAT ING PLANE SIDE VIEW
C
0.08 C e
PIN 1 INDEX AREA
b
1 4
0.10
CAB
Pin#1 ID
L
8
BOTTOM VIEW
5
8070540_A
Table 8.
Symbol
TDFN - 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data
Dimension (mm) Min. Nom. 0.75 0.02 0.20 2.00 2.00 0.50 0.45 0.55 0.65 0.018 Max. 0.80 0.05 0.25 Min. 0.028 0.000 0.006 Dimension (inches) Nom. 0.030 0.001 0.008 0.079 0.079 0.020 0.022 0.026 Max. 0.031 0.002 0.010
A A1 b D BSC E BSC e L
0.70 0.00 0.15
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Package mechanical data Figure 13. Landing pattern - TDFN - 8-lead 2 x 2 mm without thermal pad
D P
E
E1
L
b
AM00441
Table 9.
Parameter L b E E1 D P
Parameter for landing pattern - TDFN - 8-lead 2 x 2 mm package
Dimension (mm) Description Min. Contact length Contact width Max. land pattern Y-direction Contact gap spacing Max. land pattern X-direction Contact pitch 1.05 0.25 Nom. Max. 1.15 0.30
-- --
2.75 0.65 1.75 0.5
-- -- -- --
-- -- -- --
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Package mechanical data Figure 14. Carrier tape
P0 D T A0 Top cover tape B0 P2 E
STM6510
F W
K0
Center lines of cavity User direction of feed
P1
AM03073v2
Table 10.
Package
Carrier tape dimensions
W 8.00 +0.30 -0.10 D 1.50 +0.10/ -0.00 E P0 P2 F A0 2.30 0.05 B0 2.30 0.05 K0 1.00 0.05 P1 4.00 0.10 T 0.250 0.05 Unit Bulk qty.
TDFN8
1.75 4.00 2.00 3.50 0.10 0.10 0.10 0.05
mm 3000
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STM6510 Figure 15. Reel dimensions
Package mechanical data
T
40 mm min. acces hole at slot location B
D A
C
N
Full radius Tape slot in core for tape start 25 mm min width G measured at hub
AM00443
Table 11.
Tape sizes 8 mm
Reel dimensions
A max. 180 (7 inches) B min. 1.50 C 13.0 +/- 0.20 D min. 20.20 N min. 60 G 8.4 +2/-0 T max. 14.40
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Package mechanical data Figure 16. Tape trailer/leader
End
STM6510
Start
Top cover tape
No components T RA IL ER 160 mm min.
Components
100 mm min.
No components L EA D ER
400 mm min.
Sealed with cover tape
User direction of feed
AM00444
Figure 17. Pin 1 orientation
User direction of feed
AM00442
Note:
1 2
Drawings are not to scale. All dimensions are in mm, unless otherwise noted.
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STM6510
Part numbering
6
Table 12.
Example: Device type STM6510
Part numbering
Ordering information scheme
STM6510 W C A C DG 6 F
Reset (VCC monitoring threshold) voltage VRST L = 4.625 V (typ., falling) M = 4.375 V T = 3.075 V S = 2.925 V R = 2.625 V Z = 2.313 V Y = 2.188 V W = 1.665 V V = 1.575 V Smart ResetTM setup delay control (tSRC); presence of internal input pull-up on all Smart ResetTM inputs (SR0, SR1) C = 1 to 15 s, user-programmable (external capacitor); 65 k input pull-up Output type A = open-drain, active-low Reset timeout period (tREC) C = user-programmable (external capacitor) Package DG = TDFN8 - 2 x 2 x 0.75 mm, 0.5 mm pitch Temperature range 6 = -40 C to +85 C Shipping method F = ECOPACK(R) package, tape and reel
For device options currently available refer to Table 13. For other options, voltage threshold values etc. or for more information on any aspect of this device, please contact the ST sales office nearest you.
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Package marking
STM6510
7
Package marking
Table 13. Package marking
tSRC delay control CSRC CSRC CSRC Smart ResetTM inputs type AL, PU AL, PU AL, PU VRST W S R Reset tREC Topmark output type programming AL, OD AL, OD AL, OD CtREC CtREC CtREC 8WK 8SK 8RK
Part name STM6510WCACDG6F STM6510SCACDG6F STM6510RCACDG6F
Note:
AL = Active-Low, AH = Active-High; PU = with internal pull-up resistor, OD = Open-Drain. Figure 18. Package marking, top view
A
B
C
D
E
Topmark
A = dot (pin 1 reference) B = assembly plant (P) C = assembly year (Y, 0-9): 9 = 2009 etc. D = assembly work week (WW, 01 to 52): 20 = WW20 etc. E = marking area (topmark)
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Doc ID 16788 Rev 2
STM6510
Revision history
8
Revision history
Table 14.
Date 12-Feb-2010 26-Feb-2010
Document revision history
Revision 1 2 Initial release. Updated title of datasheet, Features, Applications; updated footnote 1 of Table 2; updated Table 6, 12, 13; Figure 3; Section 1.3.3; minor textual and formatting changes. Changes
Doc ID 16788 Rev 2
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STM6510
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